1. Field of the Invention
The present invention relates to an apparatus for generating a phase delay, and more specifically, to an apparatus for generating a phase delay, which can compensate a phase difference between input signals.
2. Description of the Prior Art
Many types of circuits, such as clock generators or RF transceivers, require signals with phase of high precision because imprecise signal phases have a large impact on the whole system performance. In regards to a multiphase clock generator, the precision of each output signal phase is also very important. The larger the phase error is, the larger the jitter of output clock signal(s) may be. For systems in need of precise clock signals, such jitter may result in serious performance degradation in circuits of the following stages, such as erroneous sampling operation of an ADC (analog to digital converter) or an increased bit error rate.
When designing a circuit, it is necessary to be very cautious when considering routing paths that involve signals in need of highly precise signal phases. However, because a number of factors, such as temperature, manufacturing process variations and fluctuations in supply voltage, cannot be completely controlled, conventional VLSI circuits alone usually cannot provide precise phase delays, necessitating the use of additional mechanisms to correct the shifts in signal phases.
One of the techniques of phase adjusting is, by charging/discharging a capacitor, to insert an RC delay to a signal transmitted to circuits in the next stage. In general, a plurality of switches are respectively utilized to connect/disconnect a plurality of capacitors, so as to adjust the capacitance value, and the capacitance value in conjunction with a buffer is utilized to provide an RC delay to delay the phase of the signal.
Please refer to FIG. 1. OLE_LINK1FIG. 1 shows a block diagram of such a typical apparatus 100 for generating a phase delay. OLE_LINK1 The apparatus 100 contains a plurality of capacitors, a plurality of switches, and a buffer, and is utilized to generate an output signal by delaying an input signal. By turning on different combinations of switches, the capacitance value seen at a node N of the circuit can be adjusted. Turning on more switches results in a higher capacitance value at the node N, which in turn increases the amount of phase delay in the input signal.
In order to precisely control the phase delay of the transmitted signal, it is desirable that the capacitance and the resistance of the above-mentioned plurality of switches are of such insignificant values that they can be ignored when compared to the capacitance value of the plurality of capacitors and the resistance value of the buffer. Reason being if the parasitic capacitance value and resistance value brought by the switches are too large, the amount of RC delay may deviate from designated values, which is not desirable in circuit operation.
However, along with advances in technologies, a need for even further fine control of signal phase delay emerges, which in turn necessitate the use of devices (capacitors, buffers, etc) with even smaller resistance and capacitance in facilitating the RC delay. Under such circumstances, switches implemented by MOS transistors face the following dilemma: in order to minimize the capacitance value of the switch, the size of the MOS transistor needs to be as small as possible; on the other hand, in order to minimize the resistance value of the switch, the size of the same MOS transistor needs to be as large as possible. Hence, such dilemma results in difficulties in the design of the apparatus 100.